Referring now to FIGS. 1, 2 and 3, a prior art parasitic power circuit 10 is depicted. The parasitic power circuit 10 comprises a parasitic power capacitor 12, which is used to store voltage acquired parasitically from the data or I/O input 14. A blocking device 16, in the form of a diode transistor, allows a high signal on the signal line 18 to both power a slave device 20 with a voltage VDD and charge the parasitic power capacitor 12. During a low data signal on the signal line 18, the diode-transistor 16 is reverse biased and turned off. When the diode-transistor 16 is turned off, the VDD or voltage for the slave device 20 is the voltage held on the parasitic power capacitor 12.
FIG. 2 depicts a graph of an exemplary signal on signal line 18. The signal line goes high 22 to about 1.8 volts. While the signal line 18 is high 22, the diode-transistor 16 is forward biased and turned on such that the slave device (not particularly shown) is powered by the VDD voltage 20 while at the same time the parasitic power capacitor 12 is being charged (as shown in FIG. 3 between time 0 and about 10 microseconds). When the signal line 18 goes low 24, then the diode-transistor 16 is reverse biased and turned off such that the slave device receives its VDD voltage from the energy stored in the parasitic power capacitor.
FIG. 3 shows that in the prior art circuit, if the VDD 20 voltage is not used by a slave device, the parasitic power capacitor 12 will charge to about 1.25 volts 26. The 1.25 volts is due to the voltage drop across the prior art blocking device, diode-transistor 16, which limits the maximum voltage that the parasitic power capacitor 12 can be charged to.
Generally, with data or I/O communication signals, the high state 22 is an inactive state wherein a data signal 18 is not being transmitted on the signal line 18. When the signal line 18 goes low 23, may be indicative that data is about to be transmitted on the signal line 18. Various one-wire devices are powered parasitically from the data or I/O 14 such that a single I/O 14 connection and a ground connection are needed to power circuitry within a slave device.
The prior art parasitic power circuit 10 introduces a voltage burden to the generated VDD voltage 20. The voltage burden is equal to the minimum VDD voltage that slave circuitry, being powered by the VDD voltage 20, needs to operate plus the voltage drop across the diode-transistor 16 (VBE). The channel voltage, being the difference between the low voltage 24 and the high voltage 22 of the data signal 18, must have a minimum high voltage (VIOmin) that is high enough to keep the VDD voltage 20 at a voltage level high enough for the slave circuitry to operate. The equation describing the minimum required channel voltage is:VIOmin>VBE+(VTN+VTP)wherein the VIOmin is the minimum allowable channel voltage on the signal line 18, which must be greater than the working voltage of the slave circuitry. The working voltage of the slave circuitry can be defined by VTN+VTP wherein VTN is the voltage threshold of an N device and VTP is the threshold voltage of the P devices found in the circuitry of the slave device. VTN+VTP are thus considered the minimum voltage for the slave circuit to operate correctly. This minimum voltage is added to VBE, wherein VBE is the voltage drop from the base to the emitter of the diode-transistor 16. Thus, the minimum required channel voltage on the signal line 18 must be greater than the voltage drop across the diode-transistor 16 plus the minimum operating voltage of the slave circuit that the parasitic power circuit 10 is powering.
As technology advances, the channel voltages of microprocessor and other circuitry's signal lines is decreasing from about 2.5 volts to about 1.8 volts. Thus, the prior art parasitic power circuit 10, under good conditions, may only be able to produce a VDD voltage 20 of about 1.25 volts as shown in FIG. 3. 1.25 volts may not, in various circumstances, be a high enough working voltage to meet the minimum working voltage requirement of a slave circuit and provide for some design margin. What is needed is a new parasitic power circuit that can provide a VDD voltage for powering a slave circuit at a voltage that is closer than a prior art circuit to the channel voltage of the signal line that the parasitic power is being extracted from.